FIG. 1 is a timing diagram of a read operation of a conventional non-volatile memory device. That is, FIG. 1 shows the timing of a read operation performed by a non-volatile memory device (not shown) in response to a read enable signal /RE output from a memory controller (not shown).
As shown in FIG. 1, the memory controller may receive data DATA[7:0] within each cycle of the read enable signal /RE when the data DATA[7:0] is output from the non-volatile memory device. When the non-volatile memory device outputs the data DATA[7:0] for each read cycle time tRC of the non-volatile memory device, the read/write performance of the non-volatile memory device can be maximized (which may be referred to as “1-cycle access” of the memory controller). In other words, when 1-cycle access is used, the non-volatile memory device may operate at maximum performance. According to a data sheet of specification data provided by Samsung Electronics Co., Ltd. (http://www.sec.co.kr), “tREA” may indicate a /RE access time, “tRHZ” may indicate a /RE high to output Hi-Z, and “tREH” may indicate a /RE high hold time.
The non-volatile memory device may output the data DATA[7:0] based on the read enable signal /RE. However, as the read cycle time tRC is gradually decreased (for example, to less than 25 nanoseconds), the memory controller may be unable to perform 1-cycle access. More particularly, when the read cycle time tRC is gradually decreased, the data set-up time margin and the data hold time margin may be decreased, for example, due to switching noise generated by pins related to data input/output, jitter of the read enable signal /RE used as a clock signal for outputting data, impedance of a printed circuit board (PCB), and/or delay(s) associated with a data input/output bus.